Absolute Encoder Position Protocols: BiSS-C, SSI, and SPI Compared

The output protocol of an absolute encoder determines how position data is transferred to the receiving device, servo drive, controller, or motion processor. 

Unlike incremental encoders where the interface is always RS-422 quadrature, absolute encoders use synchronous serial protocols where the receiver clocks out a position word from the encoder on demand. 

The three most common open protocols (BiSS-C, SSI, and SPI) differ in their update rate, error detection architecture, and cable length capability.

Why Serial Protocols Are Needed for Absolute Position

An absolute encoder must communicate a multi-bit position word (typically 18 to 26 bits) at each query cycle. Parallel transmission (one wire per bit) would require 18–26 signal wires for position data alone. Serial transmission multiplexes all bits onto one or two differential pairs, reducing wiring complexity.

Two basic approaches to serial transmission:

1. Synchronous clock-in, data-out: The controller provides a clock signal; the encoder shifts out the position word synchronized to the clock. This is the approach used by SSI, SPI, and BiSS-C.

2. Self-clocking encoded: The encoder transmits the position word at its own internal clock rate, with the clock embedded in the data coding. This approach requires clock recovery at the receiver.

All three protocols covered here use synchronous clock-in, data-out.

SSI (Synchronous Serial Interface)

Protocol Structure

SSI is the oldest and most widely supported absolute encoder interface. The controller provides a differential clock pair (typically RS-422 levels); the encoder shifts out position data synchronized to the clock falling edge.

Frame format:

• Leading zeros or ones (cable propagation time fill).
• Position bits (MSB first).
• Trailing bits (vendor-defined).

No standardized framing or error detection, the controller simply clocks out N bits and interprets them as a binary position word. Some vendors add a parity bit or a checksum as the last bit, but the format is not standardized.

Clock rates: Typically 100 kHz to 2 MHz, depending on cable length and encoder capability.

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Cable length limitation: At 2 MHz with standard RS-422 cable:

• Propagation delay ≈ 5 ns/m.
• Round-trip delay at 100 m ≈ 1,000 ns = 1 µs.
• At 2 MHz clock period = 500 ns, 100 m cable cannot be driven at 2 MHz.
• Maximum cable length at 2 MHz ≈ 20–30 m; at 100 kHz ≈ 300 m.

Advantages of SSI: Widely supported; simple implementation; large installed base.

Limitations: No error detection in standard form; bidirectional parameter write not supported; lower data rate than BiSS-C.

BiSS-C (Bidirectional Synchronous Serial)

Protocol Structure

BiSS-C (open standard) extends SSI with:

1. Bidirectional communication: The master can write parameters to the encoder (zero offset, direction, protocol configuration) using a second data line (MA, Master to Encoder).
2. Cyclic redundancy check (CRC): A 6-bit CRC is appended to each position word, enabling the master to detect transmission errors.
3. Status bits: Warning and error bits are included in each frame, allowing the encoder to report internal fault conditions.

Frame structure:

1. Start condition: MA line assertion.
2. Single-cycle ACK from encoder.
3. Status bits (W = warning, E = error)
4. Position bits (26-bit typical)
5. CRC6 (polynomial x⁶ + x⁴ + x² + x + 1 per CCITT standard)

Clock rates: Up to 10 MHz – the highest of the three protocols.

Position update time at 10 MHz: 26-bit position + 2 status bits + 6 CRC bits = 34 bits; at 10 MHz → 3.4 µs per read cycle. This is fast enough for 8 kHz servo control loops.

Safety extension (BiSS Safety): Adds a second CRC, sequence counter, and error injection test capability that enables the encoder-drive link to meet SIL2/PLd functional safety requirements.

Advantages of BiSS-C: Highest data rate; error detection; bidirectional parameter access; safety extension available; open standard.

SPI (Serial Peripheral Interface)

Protocol Structure

SPI is a general-purpose serial protocol used in embedded electronics for communicating between a microcontroller and peripheral chips. 

Some absolute encoders use SPI as their output interface, primarily for compact or cost-sensitive applications where the encoder is mounted very close to the receiving electronics.

SPI uses four signals:

• SCLK: clock from master.
• MOSI: master-out, slave-in (for bidirectional encoders, used to write commands).
• MISO: master-in, slave-out (position data from encoder).
• CS: chip select (activates the encoder for communication).

SPI is not a differential interface. Unlike SSI and BiSS-C (which use RS-422 differential pairs), SPI uses single-ended logic levels (typically 3.3 V or 5 V). Single-ended signals are susceptible to common-mode noise from motor drives, switching power supplies, and long cable runs.

Cable length limitation: Single-ended SPI signals are suitable only for short runs — typically < 1 m. For longer runs (servo drive cabinet to encoder at the motor), differential interfaces (SSI or BiSS-C) are required.

Advantages of SPI: Simplest hardware implementation; widely available microcontroller peripherals; low cost.

Limitations: No differential noise immunity; short cable limit; no standardized error detection.

Protocol Comparison Table

Protocol Selection Guidance

Select SSI when:

• Replacing an existing SSI-connected encoder (backward compatibility).
• Cable runs are 10–50 m at low update rates (< 200 Hz position update).
• The drive or controller only supports SSI.

Select BiSS-C when:

• High control loop bandwidth (> 2 kHz) requires fast position updates.
• Functional safety (SIL2/PLd or SIL3/PLe) is required (use BiSS Safety extension).
• Bidirectional parameter access is needed (zero offset, direction reversal).
• New system design allows specifying the interface.

Select SPI when:

• Encoder is mounted directly on the controller PCB (< 10 cm from receiver).
• System is a self-contained embedded module where cable noise is not a concern.
• Cost optimization dominates other interface requirements.

Before you go, you might want to dive deeper into 

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